Perturbation-based digital background calibration technique for pipelined ADCs

  • Yung-Hui Chung
  • Published 2014 in 2014 IEEE International Symposium on Circuits and Systems (ISCAS)

Abstract

This paper presents a perturbation-based gain and nonlinearity background calibration scheme for high-resolution pipelined analog-to-digital converters (ADCs). Two uncorrelated pseudo-random sequences are used to inject a perturbation signal into the pipeline stages and then estimate the linearity of multiplying digital-to-analog converters (MDACs). The gain and linearity errors are corrected to achieve high-resolution performance. A 14-bit pipelined ADC is simulated to verify the proposed calibration scheme. The SNDR is improved from 45 dB to 80 dB. The simulated SFDR is over 99 dB to show the linearity improvement.

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